The present invention relates generally to semiconductor and microelectronic structures and methods for fabricating these structures. More particularly, the invention relates to methods, and structures, which prevent the insulator layer from being damaged during the creation of fin field effect transistor devices.
The use of a semiconductor fin-type field effect transistor (FinFET) has been found to provide many benefits to microelectronic devices. FinFETs allow an increase in transistor density, an improvement in the electrical characteristics of individual transistors, and advancement in the overall performance of microelectronic devices. However, the processes used for the manufacture of fins for FINFET devices have presented a number of difficulties that adversely affect the physical and electrical performance of the resulting FinFET device.
During fabrication of a FinFET, a material stack is formed using processes known in the art to layer selected materials one on top of the other. Typically, a material stack intended for FinFET fabrication includes at least a substrate layer, an insulator layer and an active semiconductor layer. During manufacture of a FinFET from a material structure, a plurality of fins are formed from the material stack by applying processes, such as those known in the art as etches and cleans, to the active semiconductor layer. These processes are utilized to form a plurality of vertical semiconductor structures from the active semiconductor layer. The resulting vertical semiconductor structures are the individual fins for FinFET devices. A plurality of fins is often referred to as a fin-array, which is typically then patterned by applying further processes known in the art to remove un-needed fins. Typically the processes utilized are selected based on the chemical and physical properties of the processes, as well as the chemical and physical properties of the materials included in the material stack.
The processes used in the fabrication of fins for FinFET devices have proved capable of providing both benefits for, and defects in, the resulting fin structures. For example, processes utilized to pattern a fin-array can result in gouging the insulator layer due to the chemical properties of the processes used and the chemical composition of the insulator layer. Gouging typically creates irregular topography on the surface of the insulator layer. The presence of irregularities on the surface of the insulator layer has been found to greatly increase the likelihood of voids forming during subsequent material depositions. And the presence of voids has been known to result in the degradation of the electrical properties and obstruction of the performance of the resulting microelectronic device.
Gouging, however, is not the only problem that results when processes, such as etches and cleans, remove some of the insulator layer. Processes utilized to prepare for gate dielectric formation can also remove some of the insulator layer, thereby undercutting the fin due to the interaction between the chemical makeup of the insulator layer and the unique chemistry of the processes. Undercutting is often the result of applying etches and cleans during the formation of a gate over a fin of a FinFET, which may involve etching away semiconducting material or other material applied during manufacturing processes. Undercutting is capable of improving gate control, but can also undermine fin stability and introduce defects into the resulting FinFET structure. Undercutting has been found to cause physically weaker connections between the fin and the underlying layer, which can fatally reduce the stability of the affected fin to the point of physical failure. Undercutting can also create difficulties for subsequently removing material that becomes deposited within the undercut region, and such deposited material can significantly alter the affected fins electrical performance, such as causing gate to gate electrical shorts.